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authorPaul Mundt <lethal@linux-sh.org>2010-08-20 20:39:22 +0900
committerPaul Mundt <lethal@linux-sh.org>2010-08-20 20:39:22 +0900
commit144c7494239f12d554806439a17ad8203c7b2d3a (patch)
treedef630d167f5e25ca926faf462653075a69c7566 /arch/sh/drivers/pci/pcie-sh7786.c
parentd2d5bc58d79321bd29ed1c8c61e806ec0541e3bf (diff)
parent65c23f54c01fabae171d54c0e78df354b3709b93 (diff)
Merge branch 'sh/pci-express-integration'
Diffstat (limited to 'arch/sh/drivers/pci/pcie-sh7786.c')
-rw-r--r--arch/sh/drivers/pci/pcie-sh7786.c30
1 files changed, 18 insertions, 12 deletions
diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index 78f378731858..d053ffca8196 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -148,16 +148,11 @@ static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
unsigned int lane, unsigned int data)
{
- unsigned long phyaddr, ctrl;
+ unsigned long phyaddr;
phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) +
((addr & 0xff) << BITS_ADR);
- /* Enable clock */
- ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
- ctrl |= (1 << BITS_CKE);
- pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
-
/* Set write data */
pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);
@@ -165,20 +160,22 @@ static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
phy_wait_for_ack(chan);
/* Clear command */
+ pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);
pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);
phy_wait_for_ack(chan);
-
- /* Disable clock */
- ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
- ctrl &= ~(1 << BITS_CKE);
- pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
}
static int phy_init(struct pci_channel *chan)
{
+ unsigned long ctrl;
unsigned int timeout = 100;
+ /* Enable clock */
+ ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
+ ctrl |= (1 << BITS_CKE);
+ pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
+
/* Initialize the phy */
phy_write_reg(chan, 0x60, 0xf, 0x004b008b);
phy_write_reg(chan, 0x61, 0xf, 0x00007b41);
@@ -187,9 +184,15 @@ static int phy_init(struct pci_channel *chan)
phy_write_reg(chan, 0x66, 0xf, 0x00000010);
phy_write_reg(chan, 0x74, 0xf, 0x0007001c);
phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);
+ phy_write_reg(chan, 0xb0, 0xf, 0x00000610);
/* Deassert Standby */
- phy_write_reg(chan, 0x67, 0xf, 0x00000400);
+ phy_write_reg(chan, 0x67, 0x1, 0x00000400);
+
+ /* Disable clock */
+ ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
+ ctrl &= ~(1 << BITS_CKE);
+ pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
while (timeout--) {
if (pci_read_reg(chan, SH4A_PCIEPHYSR))
@@ -287,6 +290,9 @@ static int pcie_init(struct sh7786_pcie_port *port)
__raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
__raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0);
+ __raw_writel(memphys, chan->reg_base + SH4A_PCIEPCICONF4);
+ __raw_writel(0, chan->reg_base + SH4A_PCIEPCICONF5);
+
/* Finish initialization */
data = pci_read_reg(chan, SH4A_PCIETCTLR);
data |= 0x1;