summaryrefslogtreecommitdiff
path: root/drivers/soc
diff options
context:
space:
mode:
authorThierry Reding <treding@nvidia.com>2016-10-10 13:13:36 +0200
committerThierry Reding <treding@nvidia.com>2016-11-15 15:51:51 +0100
commit95b780b3d7e3f1900e09dfe90e959f220a8df343 (patch)
tree3c96ece1178168b03a97cdc184aed869709967d6 /drivers/soc
parent84cf85ea6ea29fc0c933a85fb3e900315759a581 (diff)
soc/tegra: pmc: Use consistent ordering of bit definitions
Bit definitions are sorted in decreasing order by offset. Apply the same ordering to all definitions. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/soc')
-rw-r--r--drivers/soc/tegra/pmc.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 01da62484e20..d57f3e0f5f27 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -45,13 +45,13 @@
#include <soc/tegra/pmc.h>
#define PMC_CNTRL 0x0
-#define PMC_CNTRL_MAIN_RST BIT(4)
-#define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
-#define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
-#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
-#define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
-#define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
#define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
+#define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
+#define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
+#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
+#define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
+#define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
+#define PMC_CNTRL_MAIN_RST BIT(4)
#define DPD_SAMPLE 0x020
#define DPD_SAMPLE_ENABLE BIT(0)