From ef9a23f358383376009bac2a0262be1fff3eda70 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Wed, 30 Mar 2022 14:15:37 +0900 Subject: dt-bindings: serial: uniphier: Use maxItems for a single clock 'maxItems' is preferred for a single entry, not 'minItems'. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kunihiko Hayashi Link: https://lore.kernel.org/r/1648617338-8600-2-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/serial') diff --git a/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml b/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml index d490c7c4b967..06353028b274 100644 --- a/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml +++ b/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml @@ -20,7 +20,7 @@ properties: maxItems: 1 clocks: - minItems: 1 + maxItems: 1 auto-flow-control: description: enable automatic flow control support. -- cgit v1.2.3-70-g09d2 From e5fe471f7156c96a9da34b25f955dae5b0dfb46a Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Wed, 30 Mar 2022 14:15:38 +0900 Subject: dt-bindings: serial: uniphier: Add "resets" property as optional UniPhier UART controller has a reset lines from system controller. Add "resets" property to fix the following warning. uniphier-ld11-global.dtb: serial@54006800: 'resets' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kunihiko Hayashi Link: https://lore.kernel.org/r/1648617338-8600-3-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation/devicetree/bindings/serial') diff --git a/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml b/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml index 06353028b274..3d01cc355778 100644 --- a/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml +++ b/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml @@ -22,6 +22,9 @@ properties: clocks: maxItems: 1 + resets: + maxItems: 1 + auto-flow-control: description: enable automatic flow control support. $ref: /schemas/types.yaml#/definitions/flag -- cgit v1.2.3-70-g09d2 From 77edd0de002813629bb3b6efd336a630fab68aa0 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 23 Mar 2022 17:36:59 +0800 Subject: dt-bindings: serial: fsl-lpuart: Add imx93 compatible string The lpuart on i.MX93 is derived from i.MX7ULP with some industrial enhancements, it uses two compatible strings, so update the compatible string for i.MX93. Acked-by: Rob Herring Signed-off-by: Peng Fan Link: https://lore.kernel.org/r/20220323093659.1722463-1-peng.fan@oss.nxp.com Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/fsl-lpuart.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/serial') diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml index ff364bd0fbac..30eaa62e1aed 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml @@ -23,7 +23,9 @@ properties: - fsl,imx8qxp-lpuart - fsl,imxrt1050-lpuart - items: - - const: fsl,imx8ulp-lpuart + - enum: + - fsl,imx93-lpuart + - fsl,imx8ulp-lpuart - const: fsl,imx7ulp-lpuart - items: - enum: -- cgit v1.2.3-70-g09d2 From 7bb301812b62809903e07ceaf5c176f20798e3c6 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Wed, 30 Mar 2022 16:40:13 +0100 Subject: dt-bindings: serial: renesas,em-uart: Document r9a09g011 bindings The Renesas RZ/V2M (r9a09g011) SoC uses a uart that is compatible with the EMMA Mobile SoC. Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220330154024.112270-3-phil.edworthy@renesas.com Acked-by: Rob Herring Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/renesas,em-uart.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/serial') diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml index e98ec48fee46..332c385618e1 100644 --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml @@ -14,7 +14,14 @@ allOf: properties: compatible: - const: renesas,em-uart + oneOf: + - items: + - enum: + - renesas,r9a09g011-uart # RZ/V2M + - const: renesas,em-uart # generic EMMA Mobile compatible UART + + - items: + - const: renesas,em-uart # generic EMMA Mobile compatible UART reg: maxItems: 1 -- cgit v1.2.3-70-g09d2 From 19401e9755313ba681e9c8f41e8c176cd95663bb Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Mon, 4 Apr 2022 23:59:36 +0530 Subject: dt-bindings: serial: Update Qualcomm geni based QUP UART bindings Similar to I2C controller, move geni based QUP UART controller binding out from parent schema to an individual binding and let parent refer to child schema later on. UART binding also stand incomplete right now similar to I2C, complete it along this process. Signed-off-by: Kuldeep Singh Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220404182938.29492-4-singh.kuldeep87k@gmail.com Signed-off-by: Greg Kroah-Hartman --- .../bindings/serial/qcom,serial-geni-qcom.yaml | 86 ++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml (limited to 'Documentation/devicetree/bindings/serial') diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml new file mode 100644 index 000000000000..05a6999808d1 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/serial/qcom,serial-geni-qcom.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Geni based QUP UART interface + +maintainers: + - Andy Gross + - Bjorn Andersson + +allOf: + - $ref: /schemas/serial/serial.yaml# + +properties: + compatible: + enum: + - qcom,geni-uart + - qcom,geni-debug-uart + + clocks: + maxItems: 1 + + clock-names: + const: se + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: qup-core + - const: qup-config + + interrupts: + minItems: 1 + items: + - description: UART core irq + - description: Wakeup irq (RX GPIO) + + operating-points-v2: true + + pinctrl-0: true + pinctrl-1: true + + pinctrl-names: + minItems: 1 + items: + - const: default + - const: sleep + + power-domains: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + serial@a88000 { + compatible = "qcom,geni-uart"; + reg = <0xa88000 0x7000>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-0 = <&qup_uart0_default>; + pinctrl-names = "default"; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + }; +... -- cgit v1.2.3-70-g09d2 From 85a503c9ea7d4978db5f98de941e6c04b44623f1 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 25 Apr 2022 15:41:57 +0900 Subject: dt-bindings: serial: renesas,hscif: Document r8a779g0 bindings R-Car V4H (R8A779G0) SoC has the R-Car Gen4 compatible HSCIF ports, so document the SoC specific bindings. Signed-off-by: Yoshihiro Shimoda Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220425064201.459633-4-yoshihiro.shimoda.uh@renesas.com Reviewed-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/renesas,hscif.yaml | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'Documentation/devicetree/bindings/serial') diff --git a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml index ee9804cd49bb..d688a07a0e29 100644 --- a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml @@ -55,6 +55,12 @@ properties: - const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2 - const: renesas,hscif # generic HSCIF compatible UART + - items: + - enum: + - renesas,hscif-r8a779g0 # R-Car V4H + - const: renesas,rcar-gen4-hscif # R-Car Gen4 + - const: renesas,hscif # generic HSCIF compatible UART + reg: maxItems: 1 @@ -113,6 +119,7 @@ if: enum: - renesas,rcar-gen2-hscif - renesas,rcar-gen3-hscif + - renesas,rcar-gen4-hscif then: required: - resets -- cgit v1.2.3-70-g09d2 From 103dcf2ea2df2669d3e4496974e6bb0911ff515f Mon Sep 17 00:00:00 2001 From: Ilpo Järvinen Date: Tue, 26 Apr 2022 15:24:41 +0300 Subject: dt_bindings: rs485: Add receiver enable polarity MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add polarity property for receiver enable. Some UARTs have separate enable pins for tx (RTS or DE) and rx (RE). As most RS485 transceivers have !RE pin, the default is active low in contrast to rs485-rts-active-low that defaults to active high. Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Ilpo Järvinen Link: https://lore.kernel.org/r/20220426122448.38997-4-ilpo.jarvinen@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/rs485.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation/devicetree/bindings/serial') diff --git a/Documentation/devicetree/bindings/serial/rs485.yaml b/Documentation/devicetree/bindings/serial/rs485.yaml index 0c9fa694f85c..f2c9c9fe6aa7 100644 --- a/Documentation/devicetree/bindings/serial/rs485.yaml +++ b/Documentation/devicetree/bindings/serial/rs485.yaml @@ -33,6 +33,11 @@ properties: description: drive RTS low when sending (default is high). $ref: /schemas/types.yaml#/definitions/flag + rs485-rx-active-high: + description: Polarity of receiver enable signal (when separate from RTS). + True indicates active high (default is low). + $ref: /schemas/types.yaml#/definitions/flag + linux,rs485-enabled-at-boot-time: description: enables the rs485 feature at boot time. It can be disabled later with proper ioctl. -- cgit v1.2.3-70-g09d2 From e4de48da57f337a0296f04885ca8b94ae61ca41a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 May 2022 15:34:57 +0200 Subject: dt-bindings: serial: renesas,hscif: R-Car V3U is R-Car Gen4 Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence move its compatible value to the R-Car Gen4 section. Signed-off-by: Geert Uytterhoeven Acked-by: Krzysztof Kozlowski Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/dd734aaa4e5e0b32864b038b79eafe72907fb99f.1651497024.git.geert+renesas@glider.be Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/renesas,hscif.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/serial') diff --git a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml index d688a07a0e29..87180d95cd4c 100644 --- a/Documentation/devicetree/bindings/serial/renesas,hscif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,hscif.yaml @@ -51,12 +51,12 @@ properties: - renesas,hscif-r8a77980 # R-Car V3H - renesas,hscif-r8a77990 # R-Car E3 - renesas,hscif-r8a77995 # R-Car D3 - - renesas,hscif-r8a779a0 # R-Car V3U - const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2 - const: renesas,hscif # generic HSCIF compatible UART - items: - enum: + - renesas,hscif-r8a779a0 # R-Car V3U - renesas,hscif-r8a779g0 # R-Car V4H - const: renesas,rcar-gen4-hscif # R-Car Gen4 - const: renesas,hscif # generic HSCIF compatible UART -- cgit v1.2.3-70-g09d2 From f26c65dacfc2a9a0da07220972727de48534b646 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 May 2022 15:34:58 +0200 Subject: dt-bindings: serial: renesas,scif: R-Car V3U is R-Car Gen4 Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence move its compatible value to the R-Car Gen4 section. Signed-off-by: Geert Uytterhoeven Acked-by: Krzysztof Kozlowski Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/c57ed00e85778380776330be6183c6861d843c22.1651497024.git.geert+renesas@glider.be Signed-off-by: Greg Kroah-Hartman --- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/serial') diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index 5d37f8f189fb..90fe45265fbc 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -60,12 +60,12 @@ properties: - renesas,scif-r8a77980 # R-Car V3H - renesas,scif-r8a77990 # R-Car E3 - renesas,scif-r8a77995 # R-Car D3 - - renesas,scif-r8a779a0 # R-Car V3U - const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2 - const: renesas,scif # generic SCIF compatible UART - items: - enum: + - renesas,scif-r8a779a0 # R-Car V3U - renesas,scif-r8a779f0 # R-Car S4-8 - const: renesas,rcar-gen4-scif # R-Car Gen4 - const: renesas,scif # generic SCIF compatible UART -- cgit v1.2.3-70-g09d2 From 4ed26f87c71f97d6551caeb2e9e533f8980e764e Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Thu, 12 May 2022 08:26:49 +0100 Subject: dt-bindings: serial: renesas,em-uart: Add RZ/V2M clock to access the registers The RZ/V2M SoC has an additional clock to access the registers. The HW manual says this clock should not be touched as it is used by the "ISP Firmware". Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring Signed-off-by: Phil Edworthy Link: https://lore.kernel.org/r/20220512072649.7879-1-phil.edworthy@renesas.com Signed-off-by: Greg Kroah-Hartman --- .../bindings/serial/renesas,em-uart.yaml | 28 ++++++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-) (limited to 'Documentation/devicetree/bindings/serial') diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml index 332c385618e1..b25aca733b72 100644 --- a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml @@ -9,9 +9,6 @@ title: Renesas EMMA Mobile UART Interface maintainers: - Magnus Damm -allOf: - - $ref: serial.yaml# - properties: compatible: oneOf: @@ -30,10 +27,31 @@ properties: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + items: + - description: UART functional clock + - description: Internal clock to access the registers clock-names: - const: sclk + minItems: 1 + items: + - const: sclk + - const: pclk + +allOf: + - $ref: serial.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g011-uart + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 required: - compatible -- cgit v1.2.3-70-g09d2