From 87ecb68bdf8a3e40ef885ddbb7ca1797dca40ebf Mon Sep 17 00:00:00 2001 From: pbrook Date: Sat, 17 Nov 2007 17:14:51 +0000 Subject: Break up vl.h. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3674 c046a42c-6fe2-441c-8c8c-71466251a162 --- hw/ppc.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 hw/ppc.h (limited to 'hw/ppc.h') diff --git a/hw/ppc.h b/hw/ppc.h new file mode 100644 index 0000000000..0a3d4ff06b --- /dev/null +++ b/hw/ppc.h @@ -0,0 +1,31 @@ +/* PowerPC hardware exceptions management helpers */ +typedef void (*clk_setup_cb)(void *opaque, uint32_t freq); +typedef struct clk_setup_t clk_setup_t; +struct clk_setup_t { + clk_setup_cb cb; + void *opaque; +}; +static inline void clk_setup (clk_setup_t *clk, uint32_t freq) +{ + if (clk->cb != NULL) + (*clk->cb)(clk->opaque, freq); +} + +clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq); +/* Embedded PowerPC DCR management */ +typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn); +typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val); +int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn), + int (*dcr_write_error)(int dcrn)); +int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, + dcr_read_cb drc_read, dcr_write_cb dcr_write); +clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq); +/* Embedded PowerPC reset */ +void ppc40x_core_reset (CPUState *env); +void ppc40x_chip_reset (CPUState *env); +void ppc40x_system_reset (CPUState *env); +void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); + +extern CPUWriteMemoryFunc *PPC_io_write[]; +extern CPUReadMemoryFunc *PPC_io_read[]; +void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); -- cgit v1.2.3-70-g09d2