diff options
| author | Zhang Rui <rui.zhang@intel.com> | 2024-03-20 13:15:08 +0800 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2024-08-29 17:31:25 +0200 |
| commit | ff418f34ba44d8ff6cea953dd79546f3e4c6c807 (patch) | |
| tree | 88fe1341b07cf4e5f00bd034d261203a9dfd2c9e | |
| parent | 7afea7bc49c5482ac11fc4488230827edc51e28a (diff) | |
ACPICA: Complete CXL 3.0 CXIMS structures
ACPICA commit eb2a2ff303416fb3f6c425d519dbcd6988dbd91f
Commit 2d8dc0383d3c9 ("Add CXL 3.0 structures (CXIMS & RDPAS) to the
CEDT table") introduces basic support for CXL XOR Interleave Math
Structure (CXIMS).
Complete the CXIMS structures.
No functional change.
Link: https://github.com/acpica/acpica/commit/eb2a2ff3
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
| -rw-r--r-- | include/acpi/actbl1.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 841ef9f22795..8cfcd1e1c177 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -567,6 +567,10 @@ struct acpi_cedt_cxims { u64 xormap_list[]; }; +struct acpi_cedt_cxims_target_element { + u64 xormap; +}; + /* 3: CXL RCEC Downstream Port Association Structure */ struct acpi_cedt_rdpas { |