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|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 NXP
*/
/dts-v1/;
#include "imx95.dtsi"
/ {
model = "NXP i.MX95 19X19 board";
compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
aliases {
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart1;
};
chosen {
stdout-path = &lpuart1;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux_cma: linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x80000000 0 0x7f000000>;
size = <0 0x3c000000>;
linux,cma-default;
reusable;
};
};
reg_m2_pwr: regulator-m2-pwr {
compatible = "regulator-fixed";
regulator-name = "M.2-power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&i2c7_pcal6524 20 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_pcie0: regulator-pcie {
compatible = "regulator-fixed";
regulator-name = "PCIE_WLAN_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <®_m2_pwr>;
gpio = <&i2c7_pcal6524 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_slot_pwr: regulator-slot-pwr {
compatible = "regulator-fixed";
regulator-name = "PCIe slot-power";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&i2c7_pcal6524 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VDD_SD2_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <12000>;
};
};
&lpi2c7 {
clock-frequency = <1000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c7>;
status = "okay";
i2c7_pcal6524: i2c7-gpio@22 {
compatible = "nxp,pcal6524";
reg = <0x22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c7_pcal6524>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio5>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
};
};
&lpuart1 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&mu7 {
status = "okay";
};
&pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_pcie0>;
status = "okay";
};
&pcie1 {
pinctrl-0 = <&pinctrl_pcie1>;
pinctrl-names = "default";
reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
vpcie-supply = <®_slot_pwr>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-3 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <®_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
&wdog3 {
fsl,ext-reset-output;
status = "okay";
};
&scmi_iomuxc {
pinctrl_i2c7_pcal6524: i2c7pcal6524grp {
fsl,pins = <
IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e
>;
};
pinctrl_lpi2c7: lpi2c7grp {
fsl,pins = <
IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e
IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e
>;
};
pinctrl_pcie1: pcie1grp {
fsl,pins = <
IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
};
|
