summaryrefslogtreecommitdiff
path: root/softmmu_template.h
diff options
context:
space:
mode:
authorYongbok Kim <yongbok.kim@imgtec.com>2015-06-01 12:13:23 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2015-06-11 10:13:28 +0100
commit3b4afc9e75ab1a95f33e41f462921093f8a109c4 (patch)
treed2f9bcad2f99fc11209b1d59993abf96700611ad /softmmu_template.h
parentbe3a8c53b4f18bcc51a462d977cc61a0f46ebb1c (diff)
softmmu: Add probe_write()
Probe for whether the specified guest write access is permitted. If it is not permitted then an exception will be taken in the same way as if this were a real write access (and we will not return). Otherwise the function will return, and there will be a valid entry in the TLB for this access. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'softmmu_template.h')
-rw-r--r--softmmu_template.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/softmmu_template.h b/softmmu_template.h
index 39f571b0ca..d42d89d541 100644
--- a/softmmu_template.h
+++ b/softmmu_template.h
@@ -548,6 +548,28 @@ glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
helper_te_st_name(env, addr, val, oi, GETRA());
}
+#if DATA_SIZE == 1
+/* Probe for whether the specified guest write access is permitted.
+ * If it is not permitted then an exception will be taken in the same
+ * way as if this were a real write access (and we will not return).
+ * Otherwise the function will return, and there will be a valid
+ * entry in the TLB for this access.
+ */
+void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
+ uintptr_t retaddr)
+{
+ int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
+ target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
+
+ if ((addr & TARGET_PAGE_MASK)
+ != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
+ /* TLB entry is for a different page */
+ if (!VICTIM_TLB_HIT(addr_write)) {
+ tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
+ }
+ }
+}
+#endif
#endif /* !defined(SOFTMMU_CODE_ACCESS) */
#undef READ_ACCESS_TYPE