diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2016-02-23 15:36:43 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-02-26 15:09:41 +0000 |
| commit | f8c88bbcda76d5674e4bb125471371b41d330df8 (patch) | |
| tree | 94a6ea0437de3b0629eba23dd6dde4e0e38a743c /target-arm/op_helper.c | |
| parent | 50866ba5a2cfe922aaf3edb79f6eac5b0653477a (diff) | |
target-arm: Raw CPSR writes should skip checks and bank switching
Raw CPSR writes should skip the architectural checks for whether
we're allowed to set the A or F bits and should also not do
the switching of register banks if the mode changes. Handle
this inside cpsr_write(), which allows us to drop the "manually
set the mode bits to avoid the bank switch" code from all the
callsites which are using CPSRWriteRaw.
This fixes a bug in 32-bit KVM handling where we had forgotten
the "manually set the mode bits" part and could thus potentially
trash the register state if the mode from the last exit to userspace
differed from the mode on this exit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1455556977-3644-4-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/op_helper.c')
| -rw-r--r-- | target-arm/op_helper.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 543d33aad2..4881e34177 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -779,7 +779,10 @@ void HELPER(exception_return)(CPUARMState *env) if (!return_to_aa64) { env->aarch64 = 0; - env->uncached_cpsr = spsr & CPSR_M; + /* We do a raw CPSR write because aarch64_sync_64_to_32() + * will sort the register banks out for us, and we've already + * caught all the bad-mode cases in el_from_spsr(). + */ cpsr_write(env, spsr, ~0, CPSRWriteRaw); if (!arm_singlestep_active(env)) { env->uncached_cpsr &= ~PSTATE_SS; |