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authorJuha Riihimäki <juha.riihimaki@nokia.com>2009-10-24 15:19:00 +0300
committerAurelien Jarno <aurelien@aurel32.net>2009-10-27 09:46:26 +0100
commit2301db49163b5a67ded15fc8bc0407903f8e23fb (patch)
treeb5b42a288e2e799bb6ee676eabf1815ed2e4d062 /target-arm
parent25aeb69b8d3cca341007a2f63d068885b3d4802b (diff)
target-arm: fix neon vshrn/vrshrn ops
In the existing code shift value is clobbered during the pass loop. This patch changes the code so that it stores the intermediate result in the target neon register directly and eliminates the need to use a temporary to hold the intermediate value thus leaving the shift value in the temporary variable intact. This is a new patch in this version of the patch series. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-arm')
-rw-r--r--target-arm/translate.c12
1 files changed, 3 insertions, 9 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 1988cc693e..3fe545d6c4 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -4680,18 +4680,12 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
else
gen_neon_narrow_satu(size - 1, tmp, cpu_V0);
}
- if (pass == 0) {
- if (size != 3) {
- dead_tmp(tmp2);
- }
- tmp2 = tmp;
- } else {
- neon_store_reg(rd, 0, tmp2);
- neon_store_reg(rd, 1, tmp);
- }
+ neon_store_reg(rd, pass, tmp);
} /* for pass */
if (size == 3) {
tcg_temp_free_i64(tmp64);
+ } else {
+ dead_tmp(tmp2);
}
} else if (op == 10) {
/* VSHLL */