diff options
| author | Leon Alrae <leon.alrae@imgtec.com> | 2016-06-09 10:46:50 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2016-07-12 09:10:14 +0100 |
| commit | 89777fd10fc3dd573c3b4d1b2efdd10af823c001 (patch) | |
| tree | 0b761b2e015b2925b09528a20cab1035a53ce79d /target-mips/helper.c | |
| parent | 19494f811a43c6bc226aa272d86300d9229224fe (diff) | |
target-mips: add exception base to MIPS CPU
Replace hardcoded 0xbfc00000 with exception_base which is initialized with
this default address so there is no functional change here.
However, it is now exposed and consequently it will be possible to modify
it from outside of the CPU.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/helper.c')
| -rw-r--r-- | target-mips/helper.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-mips/helper.c b/target-mips/helper.c index 65fbef0050..1402ff0a34 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -640,7 +640,7 @@ void mips_cpu_do_interrupt(CPUState *cs) /* EJTAG probe trap enable is not implemented... */ if (!(env->CP0_Status & (1 << CP0St_EXL))) env->CP0_Cause &= ~(1U << CP0Ca_BD); - env->active_tc.PC = (int32_t)0xBFC00480; + env->active_tc.PC = env->exception_base + 0x480; set_hflags_for_handler(env); break; case EXCP_RESET: @@ -667,7 +667,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->hflags &= ~(MIPS_HFLAG_KSU); if (!(env->CP0_Status & (1 << CP0St_EXL))) env->CP0_Cause &= ~(1U << CP0Ca_BD); - env->active_tc.PC = (int32_t)0xBFC00000; + env->active_tc.PC = env->exception_base; set_hflags_for_handler(env); break; case EXCP_EXT_INTERRUPT: @@ -849,7 +849,7 @@ void mips_cpu_do_interrupt(CPUState *cs) } env->hflags &= ~MIPS_HFLAG_BMASK; if (env->CP0_Status & (1 << CP0St_BEV)) { - env->active_tc.PC = (int32_t)0xBFC00200; + env->active_tc.PC = env->exception_base + 0x200; } else { env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff); } |